Optimization of Placements Driven By the Cost of Wire CrossingNevin

\Permission to make digital/hard copy of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for proot or commercial advantage , the copyright notice, the title of the publication and its date appear, and notice is given that copying is by permission of CBL. To copy otherwise, to republish, to post on servers or to redistribute to lists, requires prior speciic permission and/or a fee." If you choose to cite this report, please add the following entry to your bibliography database: @techreport{ 1997-TR@CBL-08-Kapur, Abstract { We conjecture that good column-based placements can be produced by minimizing two wire crossing numbers: (1) the total wire crossing of all edges between cells in the wiring channel, and (2) the maximum wire crossing on the imaginary cutlines that separate cells on the opposite ends of the channels. We leverage the canonical form of the multi-level bipartite directed graph to formalize a unit-grid model that allows us to deene and evalutate parameters such as total wire crossing, critical wire crossing, total wire length, critical wire length, critical wire density, total wire density, as well as height, width, and area of the embedded graph. We implemented a prototype placement algorithm TOCO that minimizes the cost of wire crossing, and a universal unit-grid based placement evaluator place eval. We have designed a number of statistical experiments to demonstrate the feasibility and the promise of the proposed approach. Area and performance in submicron-technology VLSI circuits are critically dominated by the interconnect. The variations in interconnect that arise after cell placement and routing, such as wire crossings, wire density, wire loading, wire length, etc., may be hard if not impossible to predict. Similarly, the interconnect models associated with the logic implementation and logic testability prior to placement and routing may change considerably after cell placement and routing. In row{based cell placement, the cost function that continues to dominate the research relates mostly to total wire-length, e.g. the simulated annealing approach 1]. The length of the interconnect in randomized and optimized placements has been formalized in 2]. Abstract placement models, such as presented in 3], also aim to minimize the channel density. The crossing number and wire area have been investigated for eeective wire lower bounds and edge length in a variety of computational VLSI circuits, using a graph-based grid model 4]. In this paper, …